1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a transistor with a gate dielectric layer that has a high dielectric constant and a level of nitrogen doping, and to a method of making the same.
2. Description of the Related Art
A conventional field effect transistor implemented in silicon typically consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate dielectric layer is positioned on the substrate over the channel region and a gate electrode composed of a conducting material, such as aluminum or doped polysilicon, is disposed on the gate dielectric layer. The gate electrode is designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. The first implant is performed self-aligned to the gate electrode to establish lightly doped drain ("LDD") structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
The gate dielectric formation aspects of conventional transistor fabrication present certain disadvantages. Silicon dioxide gate oxide layers are made as thin as possible to maximize drive current and to control short channel effects. The requirement for very thin gate oxide layers has become particularly important in sub-micron processing where process scaling has dramatically increased the potential for short channel effects. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot and cold carrier injection degradation increases. Hot and cold carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
One potential cause of carrier injection and potential dielectric breakdown is thought to occur as a result of interface traps near the Si--SiO.sub.2 interface. Interface traps are the apparent result of dangling silicon bonds at the Si--SiO.sub.2 interface. Dangling Si bonds represent sites where hot carrier injection, Fowler-Nordheim tunneling and direct tunneling can occur. Although tunneling is thought to arise as a natural consequence of the quantum mechanical nature of electrons positioned near a very thin oxide layer, dangling Si bonds appear to exacerbate the problem. Independent of the exact physical cause of carrier injection, the empirical result for very thin oxides may be gate leakage currents and/or catastrophic device failure.
Another difficulty associated with very thin conventional gate oxides is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion. The potential for boron diffusion increases with decreasing oxide thickness.
One alternative to conventional gate dielectric formation involves the use of an alternative gate dielectric material. One such alternative that has been proposed is tantalum pentoxide (Ta.sub.2 O.sub.5). Since tantalum pentoxide has a higher dielectric constant ("K") than SiO.sub.2, a gate dielectric layer composed of Ta.sub.2 O.sub.5 can have a greater thickness than a corresponding layer of SiO.sub.2, yet have approximately the same equivalent thickness as the SiO.sub.2, that is, the same equivalent thickness of oxide ("t.sub.OX "). A relatively thicker gate dielectric layer can eliminate some of the risks of carrier injection and polysilicon depletion associated with very thin SiO.sub.2 layers.
While a relatively thick layer with a thin equivalent tox is desirable, fabricating a layer of Ta.sub.2 O.sub.5 with an appropriately thin equivalent t.sub.OX can prove difficult. The problem stems from the fact that, after formation, a metal oxide layer, such as Ta.sub.2 O.sub.5, often contains residual oxygen, either in free form or loosely bonded to metal atoms. During any of the various high temperature steps that normally follow gate dielectric formation, the mobile oxygen may migrate and react with other materials, such as the underlying substrate or the overlying polysilicon gate electrode and form oxide. The oxide thus formed translates into an unwanted increase in the equivalent t.sub.OX of the gate dielectric layer and a step backward in device performance.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.